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Dual RF LDMOS Bias Controller with
Nonvolatile Memory
Table 11. Hardware Configuration Register
DATA BITS
D15*
D[14:12]*
BIT NAME
T1AVGCTL
T1LIMIT[2:0]
RESET STATE
0
000
FUNCTION
Channel 1 averaging-equation bit. This bit controls the averaging equation
for channel 1 while the device is in tracking mode. See Table 11a.
Channel 1 difference-limiter bits. Set T1LIMIT[2:0] to enable the difference
limiter for channel 1 temperature averaging. See Table 11b.
If the FIFOSTAT bit is set to 1, the ALARM output is used to monitor data
D11
FIFOSTAT
0
flow into/out of the FIFO and EEPROM while in the message and LUT
streaming modes.
ADC monitor enable bit. If ADCMON is set to 1, the result from the ADC
D10
ADCMON
0
conversion is copied into the FIFO, from where it can be read over the
serial interface. If ADCMON = 0, the result is not copied into the FIFO.
ADCMON and AVGMON cannot be active at the same time.
D[9:8]
D[7:6]
D[5:4]
D[3:2]
D[1:0]
PG2SET[1:0]
PG1SET[1:0]
CKSEL[1:0]
ADCREF[1:0]
DACREF[1:0]
00
00
00
00
00
PGA2 gain-setting bits. See Table 11c.
PGA1 gain-setting bits. See Table 11c.
Clock mode and CNVST bits. See Table 11d.
ADC reference select bits. See Table 11e.
DAC reference select bits. See Table 11f.
X = Don’t care.
*Write only.
Table 11a. Channel 1 Averaging Equation
(T1AVGCTL)
D15
0
1
CHANNEL 1 AVERAGING EQUATION
Average = average + 1/16 difference.
Average = average + 1/4 difference.
Table 11b. Channel 1 Difference-Limiter Bits (T1LIMIT[2:0])
D14
0
0
0
0
1
1
1
1
D13
0
0
1
1
0
0
1
1
D12
0
1
0
1
0
1
0
1
CHANNEL 2 DIFFERENCE-LIMITER BITS (T2LIMIT[2:0])
No limiting is applied.
Difference is limited to 1 LSB (1/8 of a degree).
Difference is limited to 3 LSBs (3/8 of a degree).
Difference is limited to 7 LSBs (7/8 of a degree).
Difference is limited to 15 LSBs (1 7/8 degrees).
Difference is limited to 31 LSBs (3 7/8 degrees).
Difference is limited to 63 LSBs (7 7/8 degrees).
Difference is limited to 127 LSBs (15 7/8 degrees).
48
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